FEATURES AND BENEFITS
SNR, 70 dBFS / SFDR, 86 dBc Sample rate up to 125 Msps Input bandwidth, 600 MHz Power dissipation, 635 mW at 80 Msps, including analog input buffer SPI Duty cycle stabilizer 12-bit pipelined ADC core Clock input divider by 2 for less jitter contribution Integrated input buffer Fast OuT of Range (OTR) detection Flexible input voltage range: 1 V (p-p) to INL ±1.25 LSB, DNL ±0.25 LSB 2 V (p-p) CMOS or LVDS DDR digital outputs Offset binary, two’s complement, gray code Pin compatible with the ADC1415S Power-down and Sleep modes series, the ADC1015S series and the ADC1115S125 HVQFN40 package NXP Semiconductors ADC1215S series ADC1215S series; input buffer; CMOS or LVDS DDR digital output 3. APPLICATIONS
Wireless and wired broadband communications Portable instrumentation Imaging systems Digital predistortion loop, power amplifier linearization Spectral analysis Ultrasound equipment Software defined radio 4. Ordering information Table 1.