BSP204A Description
P-channel enhancement mode vertical D-MOS transistor in a TO-92 variant envelope, intended for use in relay, high-speed and line transformer drivers. PINNING - TO-92 variant (BSP204) PIN 1 2 3 gate drain source DESCRIPTION handbook, halfpage BSP204; BSP204A QUICK REFERENCE DATA SYMBOL −VDS −ID RDS(on) VGS(th) PARAMETER drain-source voltage drain current drain-source on-resistance gate-source threshold voltage DC...
BSP204A Key Features
- Direct interface to C-MOS, TTL, etc
- High-speed switching
- No secondary breakdown. DESCRIPTION P-channel enhancement mode vertical D-MOS transistor in a TO-92 variant envelope, in
- TO-92 variant (BSP204) PIN 1 2 3 gate drain source DESCRIPTION