FEATURES
I Dual 14-bit resolution I 650 Msps maximum update rate I I I I I I I I I I IMD3: 80 dBc; fs = 640 Msps; fo = 96 MHz I ACPR: 71 dBc; 2 carriers WCDMA; fs = 614.4 Msps; fo = 96 MHz; PLL on Selectable 2×, 4× or 8× interpolation I Typical 0.95 W power dissipation at 4× filters interpolation Input data rate up to 160 Msps I Power-down and Sleep modes Very low noise cap-free integrated PLL I Differential scalable output current from 1.6 mA to 22 mA 32-bit programmable NCO frequency I On-chip 1.25 V reference Dual port or Interleaved data modes I External analog offset control (10-bit auxiliary DACs) 1.8 V and 3.3 V power supplies I Internal digital offset control LVDS compatible clock I Inverse (sin x) / x function Two’s complement or binary offset I Fully compatible SPI port data format 3.3 V CMOS input buffers I Industrial temperature range from −40 °C to +85 °C NXP Semiconductors DAC1405D650 Dual 14-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating 3. APPLICATIONS
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