DAC1408D650 Datasheet | NXP Semiconductors

Dual 14-bit DAC; up to 650 Msps; 2, 4 or 8 interpolating with JESD204A interface Rev. 5 - 31 January 2012 Product data sheet 1. General description The DAC1408D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier WCDMA transmitters. Because of its digital on-chip modulation, the DAC1408D650 allows the plex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. The DAC1408D650 also includes a 2, 4 or 8 clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full-scale current. The input data format is serial according to JESD204A specification. This new interface has numerous advantages over the traditional parallel one: easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew pensation. The maximum number of lanes of the DAC1408D650 is 4 and its maximum serial data rate is 3.125 Gbps. The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output clock period between several DAC devices. MDS incorporates modes: Master/slave and All slave mode. 2. Features and benefits - Dual 14-bit resolution - 650 Msps maximum update rate - Selectable 2, 4 or 8 interpolation filters - Input data rate up to 312.5 Msps - Very low-noise cap-free integrated PLL - 32-bit programmable NCO frequency - Four JESD204A serial input lanes - 1.8 V and 3.3 V power supplies - LVDS patible clock inputs - IMD3: 80 d Bc; fs = 640 Msps; fo = 140 MHz - ACPR: 71 d Bc; two carriers WCDMA; fs = 640 Msps; fo = 133 MHz - Typical 1.26 W power dissipation at 4 interpolation, PLL off and 640 Msps - Power-down mode and Sleep modes - Differential scalable...