FEATURES
FEATURES
● Digital Signal Processing Core P R E L I M I N A R Y – Upto30MillionInstructionsPerSecond(MIPS)at60MHzwith 33.3 ns instruction cycle – Single-cycle 16 × 16-bit parallel Multiply-Accumulate – 2 × 40-bit accumulators with extension byte – Fractional and integer arithmetic with support for multiprecision arithmetic – Highly parallel instruction set with unique DSP addressing modes – Nested hardware DO loops including infinite loops and DO zero loop – Two instruction LMS adaptive filter loop – Fast auto-return interrupts – Three external interrupt request pins – Three 16-bit internal data and three 16-bit internal address buses – Individual programmable wait states on the external bus for program, data, and peripheral memory spaces – Programmable absolute short addressing mode – Off-chip memory-mapped peripheral space with programmable access time and separate peripheral enable pin – Peripheral Ad
NXP Semiconductors
