DESCRIPTION
HEF4012B gates Fig.2 Pinning diagram. Fig.1 Functional diagram. HEF4012BP(N): HEF4012BD(F): HEF4012BT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES see Family Specifications January 1995 2 Philips Semiconductors Product specification Dual 4-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 70 25 20 70 30 25 60 30 20 60 30 20 135 50 35 140 60 50 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP MAX HEF4012B gates TYPICAL EXTRAPOLATION FORMULA 43 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) CL 43 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 10 ns...
NXP Semiconductors
