HEF40174B Datasheet PDF | NXP Semiconductors

NXP Semiconductors HEF40174B

The HEF40174B is a hex edge-triggered D-type flip-flop with six data inputs (D0 to D5), a clock input (CP), an overriding asynchronous master reset input (MR), and six HEF40174B MSI buffered outputs (O0 to O5). When LOW, MR resets all flip-flops (O0 to O5 = LOW) independent of CP and D0 to D5.

Part No.	HEF40174B
Datasheet	HEF40174B Download
Manufacturer	NXP Semiconductors
Description	Hex D-type flip-flop
Buy	Stock & Price

DESCRIPTION

Information on D0 to D5 is transferred to O0 to O5 on the LOW to HIGH transition of CP if MR is HIGH. Fig.1 Functional diagram. PINNING D0 to D5 CP MR O0 to O5 data inputs clock input (LOW to HIGH; edge-triggered) master reset input (active LOW) buffered outputs FUNCTION TABLE Fig.2 Pinning diagram. CP HEF40174BP(N): 16-lead DIL; plastic (SOT38-1) HEF40174BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF40174BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition X INPUTS D H L X X MR H H H L OUTPUT O H L no change L This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated...