DESCRIPTION
HEF4021B MSI Each register stage is a D-type master-slave flip-flop with a set direct/clear direct input. Information on P0 to P7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. HEF4021BP(N): HEF4021BD(F): HEF4021BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications PINNING PL P0 to P7 DS CP O5 to O7 parallel load input parallel data inputs serial data input clock input (LOW to HIGH edge-triggered) buffered parallel outputs from the last three stages January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to forc...
NXP Semiconductors
