HEF4073B Datasheet | NXP Semiconductors

DESCRIPTION The HEF4073B provides the positive triple 3-input AND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. HEF4073B gates Fig.2 Pinning diagram. HEF4073BP(N): 14-lead DIL; plastic (SOT27-1) HEF4073BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4073BT(D): 14-lead SO; plastic Fig.1 Functional diagram. (SOT108-1) ( ): Package Designator North America Fig.3 Logic diagram (one gate). FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 Philips Semiconductors Product specification Triple 3-input AND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 p F; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 t TLH t THL t PLH t PHL 55 25 20 45 20 15 60 30 20 60 30 20 110 50 40 90 40 30 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX. HEF4073B gates TYPICAL EXTRAPOLATION FORMULA 23 ns + (0,55 ns/p F) CL 14 ns + (0,23 ns/p F) CL 12 ns + (0,16 ns/p F) CL 13 ns + (0,55 ns/p F) CL 9 ns + (0,23 ns/p F) CL 7 ns + (0,16 ns/p F) CL 10 ns + (1,0 ns/p F) CL 9 ns + (0,42 ns/p F) CL 6 ns + (0,28 ns/p F) CL 10 ns + (1,0 ns/p F) CL 9 ns + (0,42 ns/p F) CL 6 ns + (0,28 ns/p F) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 600 fi + ∑ (fo CL) × VDD2 2700 fi + ∑ (fo CL) × VDD 8400 fi + ∑ (fo CL) × VDD 2 2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (p F) ∑ (fo CL) = sum of outputs VDD = supply voltage (V) January...