FEATURES
The following table shows the chip features organized by functions. Table 1. i.MX RT700 features Feature Module Arm platform and debug CPU0 DESCRIPTION
● One Compute Domain CPU - Arm Cortex-M33 processor with Trustzone and built-in: — Nested Vectored Interrupt Controller (NVIC): NVIC (CPU0) implement a relocatable vector table supporting external interrupts, a single non-maskable interrupt (NMI), and priority levels. — Non-maskable interrupt (NMI) input — Memory Protection Unit (MPU): MPUs (CPU0) provides support for eight unified protection regions, overlapping protection regions with ascending region priority, and access permissions. MPU mismatches and permission violations invoke the Hard Fault handler. — Hardware Floating Point Unit (FPU): FPU (CPU0) is singleprecision floating point computation unit compliant to the IEEE Standard for Floating-Point Arithmetic (IEEE 754). — ETM Trace — System Tick Timer (SysTick): See the ARMv8M Architecture Reference Manual for more information about this system timer.
NXP Semiconductors
