IP4856CX25 Datasheet | NXP Semiconductors

description The device is an SD 3.0-pliant 6-bit bidirectional dual voltage level translator. It is designed to interface between a memory card operating at 1.8 V or 2.9 V signal levels and a host with a fixed nominal supply voltage of 1.7 V to 3.6 V. The device supports SD 3.0, SDR104, SDR50, DDR50, SDR25, SDR12 and SD 2.0 high-speed (50 MHz) and default-speed (25 MHz) modes. The device has an integrated voltage selectable low dropout regulator to supply the card-side I/Os, built-in EMI filters and robust ESD protections (IEC 61000-4-2, level 4). 2. Features and benefits - Supports up to 208 MHz clock rate - Feedback channel for clock synchronization - SD 3.0 specification-pliant voltage translation to support SDR104, SDR50, DDR50, SDR25, SDR12, high-speed and default-speed modes - 100 m A low dropout voltage regulator to supply the card-side I/Os - Low power consumption by push-pull output stage with break-before-make architecture - Integrated pull-up and pull-down resistors: no external resistors required - Integrated EMI filters suppress higher harmonics of digital I/Os - Integrated 8 k V ESD protection according to IEC 61000-4-2, level 4 on card side - Level shifting buffers keep ESD stress away from the host (zero-clamping concept) - 25-ball WLCSP; pitch 0.4 mm 3. Applications - Smartphones - Mobile handsets - Digital cameras - Tablet PCs - Laptop puters - SD, MMC or micro SD card readers 4. Ordering information Table 1. Ordering information Type number Package Name IP4856CX25/C WLCSP25 Description wafer level chip-size package with back side coating; 25 bumps (5  5); typical size: 2.05 mm  2.05 mm  0.51 mm Version - NXP Semiconductors 5. Block diagram IP4856CX25/C SD 3.0-pliant memory card integrated dual voltage level translator 96833/< 96833/< 9&&$ 6(/ (1$%/( &/.B,1 &/.B)%...