FEATURES
I 128-bit wide interface/accelerator enables high-speed 60 MHz operation. N 32 kB to 40 kB of on-chip static RAM and 512 kB of on-chip flash memory. I USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM. N An additional 8 kB of on-chip RAM accessible to USB by DMA (LPC2158 only). I 32 segment × 4 backplane LCD controller supports from 1 to 4 backplanes. I Single 10-bit DAC provides variable analog output. I Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input. I Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s), SPI and SSP with buffering and variable data length capabilities. I Single power supply chip with POR and BOD circuits: N CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads. I 100-pin LQFP package with 38 microcontroller I/O pins minimum. I Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization.
NXP Semiconductors
