NXP Semiconductors LS1046A
SoC
FEATURES
● LS1046A has four cores and LS1026A has two cores● Four 32-bit/64-bit Arm® Cortex®-v8 A72 CPUs – Arranged as a single cluster of four cores sharing a single 2 MB L2 cache – Up to 1.8 GHz operation – Single-threaded cores with 32 KB L1 data cache and 48 KB L1 instruction cache
● Hierarchical interconnect fabric – Up to 700 MHz operation
● One 32-bit/64-bit DDR4 SDRAM memory controller with ECC and interleaving support – Up to 2.1 GT/s
● Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: – Packet parsing, classification, and distribution (FMan) – Queue management for scheduling, packet sequencing, and congestion management (QMan) – Hardware buffer management for buffer allocation and de-allocation (BMan) – Cryptography acceleration (SEC) – IEEE 1588™ support
● Two RGMII interfaces
● Eight SerDes lanes for high-speed peripheral interfaces – Three PCI Express 3.0 controllers – One Serial ATA (SATA 6 Gbit/s) controller – Up to two X...