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Freescale Semiconductor Data Sheet: Technical Data
MCF5441x ColdFire Microprocessor Data Sheet
• Version 4 ColdFire Core with EMAC and MMU
• Up to 385 Dhrystone 2.1 MIPS @ 250 MHz • 8 KB instruction cache and 8 KB data cache • 64 KB internal SRAM dual-ported to
processor local bus and other crossbar switch masters • System boot from NOR, NAND, SPI flash, EEPROM, or FRAM • Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters • 64-channel DMA controller • SDRAM controller supporting full-speed operation from a single x8 DDR2 component up to 250 MHz • 32-bit FlexBus external memory interface for RAM, ROM, MRAM, and programmable logic • USB 2.0 host controller • USB 2.