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MPC5510 - Microcontroller

Key Features

  • Single issue, 32-bit CPU core complex (e200z1).
  • Compliant with the Power Architecture™ embedded category.
  • Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction.
  • Up to 1.5-Mbyte on-chip flash with flash control unit (FCU).
  • Up to 80 Kbytes on-chip SRAM.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NXP Semiconductors Data Sheet: Technical Data Document Number: MPC5510 Rev. 5, 7/2019 MPC5510 MPC5510 Microcontroller Family Data Sheet MMAAPPBBGGAA––220285 1175mmmmxx1175mmmm QFNL1Q2 FP–144 ##_m2m0 _mxm_#x#m20mmm SOT-343R ##_mm_x_##mm TBD LQFP–176 PKG2-4TBmDm x 24 mm ## mm x ## mm MPC5510 Family Features • Single issue, 32-bit CPU core complex (e200z1) – Compliant with the Power Architecture™ embedded category – Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. • Up to 1.