MPC5777M Datasheet | NXP Semiconductors

NXP Semiconductors Data Sheet: Technical Data Document Number: MPC5777M Rev. 6, 06/2016 MPC5777M Microcontroller Data Sheet 416 TEPBGA 27mm x 27 mm 512 TEPBGA 25 mm x 25 mm - Three main CPUs, single issue, 32-bit CPU core plexes (e200z7), one of which is a dedicated lockstep core. - Power Architecture® embedded specification pliance - Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction - Single-precision floating point operations - 16 KB Local instruction RAM and 64 KB local data RAM - 16 KB I-Cache and 4 KB D-Cache - I/O Processor, dual issue, 32-bit CPU core plex (e200z4), with - Power Architecture embedded specification pliance - Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction - Single-precision floating point operations - Lightweight Signal Processing Auxiliary Processing Unit (LSP APU) instruction support for digital signal processing (DSP) - 16 KB Local instruction RAM and 64 KB local data RAM - 8 KB I-Cache - 8640 KB on-chip flash - Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation - 404 KB on-chip general-purpose SRAM including 64 KB standby RAM (+ 192 KB data RAM included in the CPUs). Of this 404 KB, 64 KB can be powered by a separate supply so the contents of this portion can be preserved when the main MCU is powered down. - Multichannel direct memory access controllers (e DMA): 2 x 64 channels per e DMA (128 channels total) - Triple Interrupt controller (INTC) - Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for putational shell - Dual crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters with end-to-end ECC - Hardware Security Module (HSM) to provide robust integrity checking of flash memory -...