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Freescale Semiconductor Data Sheet
Document Number: MSC8251 Rev. 7, 08/2013
MSC8251
Single-Core Digital Signal Processor
FC-PBGA–783 29 mm × 29 mm
• One StarCore SC3850 DSP subsystems, with an SC3850 DSP core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, unified 512 Kbyte L2 cache configurable as M2 memory in 64 Kbyte increments, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, low-power Wait, Stop, and power-down processing modes, and ECC/EDC support.
MSC8251 Datasheet
