P2020
Key Features
- Dual high-performance Power Architecture® e500 cores
- 512 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory
- High-Speed USB controller (USB 2.0) – Host and device support – Enhanced host controller interface (EHCI) – ULPI interface to PHY
- Enhanced secure digital host controller (SD/MMC) Enhanced Serial peripheral interface (eSPI)
- Integrated security engine – Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi – XOR acceleration
- 64-bit DDR2/DDR3 SDRAM memory controller with ECC support
- Programmable interrupt controller (PIC) compliant with OpenPIC standard
- Two four-channel DMA controllers
- Two I2C controllers, DUART, timers
- Enhanced local bus controller (eLBC)
