P5020 Overview
Key Features
- CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints
- 2-Mbyte CoreNet platform cache with ECC (one on the P5010)
- One 10-Gigabit Ethernet (XAUI) controller
- Five 1-Gigabit Ethernet controllers – 1 Gb/s SGMII, 2.5 Gb/s SGMII and RGMII interfaces
- Two 64-bit DDR3/3L SDRAM memory controllers with ECC (one on the P5010)
- Multicore programmable interrupt controller (MPIC)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Two 4-channel DMA engines
- Enhanced local bus controller (eLBC)
