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P5020 - QorIQ integrated communication processor

Datasheet Summary

Features

  • Two e5500 Power Architecture cores (one on the P5010).
  • Each core has a backside 512-Kbyte L2 Cache with ECC.
  • Three levels of instructions: User, Supervisor, and Hypervisor.
  • Independent boot and reset.
  • Secure boot capability.
  • CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints.
  • 2-Mbyte CoreNet platform cache with ECC (one on the P5010).
  • One 10-Gigabit Ethernet (XAUI) controller.

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Datasheet preview – P5020

Datasheet Details

Part number P5020
Manufacturer NXP
File Size 3.19 MB
Description QorIQ integrated communication processor
Datasheet download datasheet P5020 Datasheet
Additional preview pages of the P5020 datasheet.
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Full PDF Text Transcription

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Freescale Semiconductor Data Sheet: Technical Data QorIQ P5020/P5010 Data Sheet Document Number: P5020 Rev. 1, 03/2015 P5020/P5010 FC-PBGA–1295 37.5 mm × 37.5 mm The P5020 and P5010 QorIQ integrated communication processor combines Power Architecture® processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, wireless infrastructure, and aerospace applications. This chip can be used for combined control, data path, and application layer processing in routers, switches, base station controllers, and general-purpose embedded computing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while also greatly simplifying board design.
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