P82B96 Datasheet | NXP Semiconductors

description The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface between the normal I2C-bus and a range of other bus configurations. It can interface I2Cbus logic signals to similar buses having different voltage and current levels. For example, it can interface to the 350 μA SMBus, to 3.3 V logic devices, and to 15 V levels and/or low-impedance lines to improve noise immunity on longer bus lengths. It achieves this interface without any restrictions on the normal I2C-bus protocols or clock speed. The IC adds minimal loading to the I2C-bus node, and loadings of the new bus or remote I2C-bus nodes are not transmitted or transformed to the local node. Restrictions on the number of I2C-bus devices in a system, or the physical separation between them, are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bidirectional signal line with I2C-bus properties. 2 Features - Bidirectional data transfer of I2C-bus signals - Isolates capacitance allowing 400 p F on Sx/Sy side and 4000 p F on Tx/Ty side - Tx/Ty outputs have 60 m A sink capability for driving low-impedance or high capacitive buses - 400 k Hz operation over at least 20 meters of wire (see AN10148) - Supply voltage range of 2 V to 15 V with I2C-bus logic levels on Sx/Sy side independent of supply voltage - Splits I2C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths. - Low power supply current - ESD protection exceeds 3500 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 - Latch-up free (bipolar process with no latching structures) - Packages offered: SO8 and TSSOP8 3 Applications -...