P83C557E6 Description
The P8xC557E6 has the same instruction set as the 80C51. Three versions of the derivative exist: For systems that require extra capability the P8xC557E6 can be expanded using standard TTL patible memories and logic.
P83C557E6 Key Features
- 80C51 central processing unit
- 48 K × 8 ROM, expandable externally to 64 Kbytes
- ROM Code protection
- 1536 × 8 RAM, expandable externally to 64 Kbytes
- Two standard 16-bit timer/counters
- An additional 16-bit timer/counter coupled to four capture registers
- A 10-bit ADC with eight multiplexed analog inputs and
- Two 8-bit resolution, pulse width modulation outputs
- Five 8-bit I/O ports plus one 8-bit input port shared with analog
- I2C-bus serial I/O port with byte oriented master and slave