P83CL580 Datasheet | NXP Semiconductors

FEATURES GENERAL DESCRIPTION ROMless version: P80CL580 APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM FUNCTIONAL DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION OVERVIEW General CPU timing MEMORY ORGANIZATION Program Memory Data Memory Special Function Registers (SFRs) Addressing I/O FACILITIES Ports Port options Port 0 options SET/RESET options TIMERS/EVENT COUNTERS Timer 0 and Timer 1 Timer T2 Timer/Counter 2 Control Register (T2CON) Watchdog Timer PULSE WIDTH MODULATED OUTPUT Prescaler Frequency Control Register (PWMP) Pulse Width Register (PWM0) ANALOG-TO-DIGITAL CONVERTER (ADC) ADC Control Register (ADCON) REDUCED POWER MODES Idle mode Power-down mode Wake-up from Power-down mode Status of external pins Power Control Register (PCON) 15 15.1 15.2 15.3 15.4 16 16.1 16.2 16.3 17 17.1 17.2 17.3 18 19 19.1 19.2 20 21 22 23 24 25 26 26.1 26.2 26.3 26.4 27 28 29 P80CL580; P83CL580 I2C-BUS SERIAL I/O Serial Control Register (S1CON) Serial Status Register...