P89V662 Datasheet | NXP Semiconductors

P89V660/662/664 8-bit 80C51 5 V low power 16 k B/32 k B/64 k B flash microcontroller with 512 B/1 k B/2 k B RAM, dual I2C-bus, SPI Rev. 3.1 - 17 October 2011 Product data sheet 1. General description The P89V660/662/664 are 80C51 microcontrollers with 16 k B/32 k B/64 k B flash and 512 B/1 k B/2 k B of data RAM. These devices are designed to be drop-in and software patible replacements for the P89C660/662/664 devices. Both the In-System Programming (ISP) and In-Application Programming (IAP) boot codes are upward patible. Additional Features of the P89V660/662/664 devices when pared to the P89C660/662/664 devices are the inclusion of a secondary 100 k Hz byte-wide I2C-bus interface, an SPI interface, four addition I/O pins (Port 4), and the ability to erase code memory in 128-byte pages. The IAP capability bined with the 128-byte page size allows for efficient use of the code memory for non-volatile data storage. 2. Features and benefits 2.1 Principal Features - Dual 100 k Hz byte-wide I2C-bus interfaces - 128-byte page erase for efficient use of code memory as non-volatile data storage - 0 MHz to 40 MHz operating frequency in 12x mode, 20 MHz in 6x mode - 16 k B/32 k B/64 k B of on-chip flash user code memory with ISP and IAP - 512 B/1 k B/2 k B RAM - SPI (Serial Peripheral Interface) and enhanced UART - PCA (Programmable Counter Array) with PWM and Capture/pare functions - Three 16-bit timers/counters - Four 8-bit I/O ports, one 4-bit I/O port - Watch Dog Timer (WDT) 2.2 Additional Features - 30 ms page erase, 150 ms block erase - Support for 6-clock (default) or 12-clock mode selection via ISP or parallel programmer - PLCC44 and TQFP44 packages - Ten interrupt sources with four priority levels - Second DPTR register - Low EMI mode (ALE inhibit) - Power-down mode with external interrupt wake-up NXP...