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PCA9515A - I2C-bus repeater

General Description

The PCA9515A is a CMOS integrated circuit intended for application in I2C-bus and SMBus systems.

Key Features

  • 2-channel, bidirectional buffer.
  • I2C-bus and SMBus compatible.
  • Active HIGH repeater enable input.
  • Open-drain input/outputs.
  • Lock-up free operation.
  • Supports arbitration and clock stretching across the repeater.
  • Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters.
  • Powered-off high-impedance I2C-bus pins.
  • Operating supply voltage range of 2.3 V to 3.6 V.
  • 5.5 V tolerant I2C-bus and enable pins NXP Semiconductors PCA9515A.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PCA9515A I2C-bus repeater Rev. 5 — 23 March 2012 Product data sheet 1. General description The PCA9515A is a CMOS integrated circuit intended for application in I2C-bus and SMBus systems. While retaining all the operating modes and features of the I2C-bus system, it permits extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9515A enables the system designer to isolate two halves of a bus, thus more devices or longer length can be accommodated. It can also be used to run two buses, one at 5 V and the other at 3.