PCA9516 Datasheet | NXP Semiconductors

DESCRIPTION The PCA9516 is a Bi CMOS integrated circuit intended for application in I2C and SMBus systems. While retaining all the operating modes and features of the system, it permits extension of the I2C bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling five buses of 400 p F. The I2C bus capacitance limit of 400 p F restricts the number of devices and bus length. Using the PCA9516 enables the system designer to divide the bus into five segments off of a hub where any segment to segment transition sees only one repeater delay. It can also be used to run different buses at 5 V and 3.3 V or 400 k Hz and 100 k Hz buses where the 100 k Hz bus is isolated when 400 k Hz operation of the other bus is required. I2C SDA1 EN1 SCL2 SDA2 GND SU01395 Figure 1. Pin configuration PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL SCL0 SDA0 SCL1 SDA1 EN1 SCL2 SDA2 GND EN2 SCL3 SDA3 EN3 SCL4 SDA4 EN4 VCC FUNCTION Serial clock bus 0 Serial data bus 0 Serial clock bus 1 Serial data bus 1 Active High Bus 1 enable Input Serial clock bus 2 Serial data bus 2 Supply ground Active High Bus 2 enable Input Serial clock bus 3 Serial data bus 3 Active High Bus 3 enable Input Serial clock bus 4 Serial data bus 4 Active High Bus 4 enable Input Supply power FEATURES - 5 channel, bi-directional buffer - I2C-bus and SMBus patible - Active high individual repeater enable input - Open-drain input/outputs - Lock-up free operation - Supports arbitration and clock stretching across the repeater - Acmodates standard mode and fast mode I2C devices and multiple masters - Powered-off high impedance I2C pins - Operating supply voltage range of 3.0 V to 3.6 V - 5 V tolerant I2C and enable pins - 0 to 400 k Hz clock frequency1 - ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101. - Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 m A. - Package offerings: SO and TSSOP ORDERING...