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PCA9665A - Fm+ parallel bus to I2C-bus controller

Download the PCA9665A datasheet PDF. This datasheet also covers the PCA9665 variant, as both devices belong to the same fm+ parallel bus to i2c-bus controller family and are provided as variant models within a single manufacturer datasheet.

General Description

The PCA9665/PCA9665A serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus system to communicate bidirectionally with the I2C-bus.

Key Features

  • Parallel-bus to I2C-bus protocol converter and interface.
  • Both master and slave functions.
  • Multi-master capability.
  • Internal oscillator trimmed to 15 % accuracy reduces external components.
  • 1 Mbit/s and up to 25 mA SCL/SDA IOL (Fast-mode Plus (Fm+)) capability.
  • I2C-bus General Call capability.
  • Software reset on parallel bus.
  • 68-byte data buffer.
  • Operating supply voltage: 2.3 V to 3.6 V.
  • 5 V tolerant I/Os.
  • Standard-mode and Fast-mode I2C-bus.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PCA9665_NXPSemiconductors.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PCA9665; PCA9665A Fm+ parallel bus to I2C-bus controller Rev. 4 — 29 September 2011 Product data sheet 1. General description The PCA9665/PCA9665A serves as an interface between most standard parallel-bus microcontrollers/microprocessors and the serial I2C-bus and allows the parallel bus system to communicate bidirectionally with the I2C-bus. The PCA9665/PCA9665A can operate as a master or a slave and can be a transmitter or receiver. Communication with the I2C-bus is carried out on a Byte or Buffered mode using interrupt or polled handshake. The PCA9665/PCA9665A controls all the I2C-bus specific sequences, protocol, arbitration and timing with no external timing element required.