PCF5083 Datasheet | NXP Semiconductors

FEATURES GENERAL DESCRIPTION APPLICATIONS ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pinning description OVERVIEW OF THE GSM CHIP SET General The role of the PCF5083 FUNCTIONAL DESCRIPTION TIMER CORE Clock generator ON/OFF Logic Mobile switch-on procedure Mobile switch-off procedure OFF/Watchdog Timer Timing Generator The Quarterbit Counter Normal Mode Sleep Mode RF-IC Interface Bus Frequency Setting Channel Gain Control Channel Immediate Control Channel Operation Modes and Control Registers IOM®-2 Interface IOM®-2 Clock Generation IOM®-2 Master Unit Monitor Channel Transmitter Protocol Monitor Channel Receiver Protocol mand/Indication Channel Transmitter mand/Indication Channel Receiver Audio Interface External IOM®-2 Interface MMI Interface RS232 Interface MMI power-down Interface General purpose parallel I/O-port Real Time Clock Setting the real time clock DESCRIPTION OF THE DSP CORE Interface description Baseband Digitizer Interface GMSK Modulator Interface 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.1.8 9.1.9 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.3 9.3.1 9.3.2 9.4 9.4.1 9.4.2 9.4.3 9.4.4 10 10.1 10.2 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Audio and Data Interface Audio interface Terminal adaptor interface for data services System controller interface Event Counter Clock Usage of General Purpose I/O Pins Power saving modes Message Interface to the System Controller Execution of GSM baseband procedures No Operation (NOP) mand Soft resetting the DSP Error handling GSM baseband procedures Procedure description Performance of GSM baseband procedures Software applications Receiving a CCH block Transmitting a CCH block FB search for timing synchronization Processing a TCH/FS multiframe MICROCONTROLLER INTERFACE Register Set for the Timer Core Interrupt Logic RESET JTAG TEST INTERFACE TEST AND EMULATION MODES LIMITING VALUES DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave...