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PCK12429 - 25-400 MHz differential PECL clock generator

General Description

The internal oscillator uses the external quartz crystal as the basis of its frequency reference.

The output of the reference oscillator is divided by 16 before being sent to the phase detector.

The VCO output is scaled by a divider that is configured by either the serial or parallel interfaces.

Key Features

  • 25 to 400 MHz differential PECL outputs.
  • ±25 ps peak-to-peak output jitter.
  • Fully integrated phase-locked loop.
  • Minimal frequency over-shoot.
  • Synthesized architecture.
  • Serial 3-wire interface.
  • Parallel interface for power-up.
  • Quartz crystal interface.
  • Package offer: SO28, PLCC28, and LQFP32.
  • Operates from 3.3 V power supply.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS PCK12429 25–400 MHz differential PECL clock generator Product data Supersedes data of 2002 Mar 15 2002 Jun 03 Philips Semiconductors Philips Semiconductors Product data 25–400 MHz differential PECL clock generator PCK12429 INTRODUCTION The PCK12429 is a general purpose synthesized clock source targeting applications that require both serial and parallel interfaces. The differential PECL output can be configured to be the VCO frequency divided by 1, 2, 4, or 8. With the output configured to divide the VCO frequency by 2, and with a 16.000 MHz external quartz crystal used to provide the reference frequency, the output frequency can be specified in 1 MHz steps. The PLL loop filter is fully integrated so that no external components are required. VCO control voltage.