PHF14NQ20T Datasheet | NXP Semiconductors

FEATURES - ’Trench’ technology - Low on-state resistance - Fast switching SYMBOL d QUICK REFERENCE DATA VDSS = 200 V ID = 7.6 A g RDS(ON) ≤ 230 mΩ s GENERAL DESCRIPTION N-channel enhancement mode field-effect power transistor in a plastic full pack envelope using ’trench’ technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHX14NQ20T is supplied in the SOT186A (FPAK) conventional leaded package. PINNING PIN 1 2 3 case gate drain source isolated DESCRIPTION SOT186A (FPAK) case SOT186 (FPAK) case 1 2 3 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 150˚C Tj = 25 ˚C to 150˚C; RGS = 20 kΩ Ths = 25 ˚C; VGS = 10 V Ths = 100 ˚C; VGS = 10 V Ths = 25 ˚C Ths = 25 ˚C MIN. - 55 MAX. 200 200 ± 20 7.6 4.8 30 30 150 UNIT V V V A A A W ˚C November 2000 Rev 1.100 Philips Semiconductors Product specification N-channel Trench MOS transistor PHX14NQ20T , PHF14NQ20T AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Peak non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 14 A; tp = 38 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer to fig 15 MIN. MAX. 70 UNIT m J - 14 THERMAL RESISTANCES SYMBOL PARAMETER Rth j-hs Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT186A package, in free air TYP. MAX. UNIT 55 4.17 K/W K/W ELECTRICAL CHARACTERISTICS Tj= 25˚C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs IGSS IDSS Qg(tot) Qgs Qgd...