PHP18NQ20T Datasheet | NXP Semiconductors

FEATURES - ’Trench’ technology - Low on-state resistance - Fast switching - Low thermal resistance SYMBOL d QUICK REFERENCE DATA VDSS = 200 V ID = 16 A g RDS(ON) ≤ 180 mΩ s GENERAL DESCRIPTION N-channel, enhancement mode field-effect power transistor using Trench technology, intended for use in off-line switched mode power supplies, T.V. and puter monitor power supplies, d.c. to d.c. converters, motor control circuits and general purpose switching applications. The PHP18NQ20T is supplied in the SOT78 (TO220AB) conventional leaded package. The PHB18NQ20T is supplied in the SOT404 (D2PAK) surface mounting package. PINNING PIN 1 2 3 tab gate drain1 source drain DESCRIPTION SOT78 (TO220AB) tab SOT404 (D2PAK) tab 1 23 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 175˚C; RGS = 20 kΩ Tmb = 25 ˚C; VGS = 10 V Tmb = 100 ˚C; VGS = 10 V Tmb = 25 ˚C Tmb = 25 ˚C MIN. - 55 MAX. 200 200 ± 20 16 11 64 136 175 UNIT V V V A A A W ˚C 1 It is not possible to make connection to pin:2 of the SOT404 package August 1999 1 Rev 1.000 Philips Semiconductors Product specification N-channel Trench MOS™ transistor PHP18NQ20T, PHB18NQ20T AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Peak non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 14 A; tp = 100 µs; Tj prior to avalanche = 25˚C; VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer to fig;15 MIN. MAX. 180 UNIT m J - 16 THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS MIN. SOT78...