SAA7112 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET SAA7112 Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN) Preliminary specification File under Integrated Circuits, IC22 1996 Jun 20 Philips Semiconductors Preliminary specification Decoder with High-Performance Scaler (HPS) for Image Port (PELICAN) Features The PELICAN SAA7112 is a video capture device for application at the image port of a VGA controller, with following feature highlights: Video Decoder - Six analog inputs, internal analog source selectors, (e.g. 6 × CVBS or(2 × YC and 2 × CVBS) or (1 × YC and 4 × CVBS) - Two analog preprocessing channels, including built in analog anti-alias filters - Fully programmable static gain for the main channels or Automatic Gain Control (AGC) for the selected CVBS/Y channel - Two 8 bit video CMOS Analog-to-Digital Converters (ADCs) - Automatic Clamp Control (ACC) for CVBS, Y and C - Switchable white peak control - On-chip line locked clock generation in accordance with CCIR-601 - Digital PLL for synchronization and clock generation from all standards and non-standard video sources, e.g. consumer grade VTR - Requires only one crystal (32.11 MHz) for all standards - Horizontal and vertical sync detection - Automatic detection of 50/60Hz field frequency, and automatic switching between standards PAL and NTSC - Luminance and chrominance signal processing for PAL BGHI, PAL N, PAL M, NTSC M, NTSC N, NTSC 4.43 and SECAM - User programmable luminance peaking or aperture correction - Cross-colour reduction for NTSC by chrominance bination filtering - PAL delay line for correcting PAL phase errors - Real time status information output (RTCO) - Independent Brightness Contrast Saturation (BCS) adjustment for decoder part. Video Scaler - Horizontal and vertical down-scaling and up-scaling to randomly sized windows - Horizontal and vertical scaling range: 2 (zoom) to 1⁄64 (icon); vertical zoom might be restricted - Anti-alias- and accumulating filter for horizontal...