SAA7125 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET SAA7124; SAA7125 Digital Video Encoder (ECO-DENC) Preliminary specification File under Integrated Circuits, IC22 1996 Nov 07 Philips Semiconductors Preliminary specification Digital Video Encoder (ECO-DENC) Features - Monolithic CMOS 5 V device - Digital PAL/NTSC encoder - System pixel frequency 13.5 MHz - Accepts MPEG decoded data on 8-bit wide input port. Input data format Cb, Y, Cr etc. “(CCIR 656)” - Four DACs for CVBS (10-bit resolution), RGB (9-bit resolution) operating at 27 MHz; RGB sync on CVBS - Optionally 2 times CVBS and Y, C (all 10-bit resolution) available simultaneously - Closed captioning encoding - On-chip YUV to RGB dematrix optionally to be by-passed for Cr, Y, Cb output on RGB DACs - Fast I2C-bus control port (400 k Hz) - Encoder can be master or slave - Programmable horizontal and vertical input synchronization phase, via input pins or auxiliary codes at MP data port - Programmable horizontal sync output phase - Internal 100/75 Colour Bar Generator (CBG) - Macrovision Pay-per-View copy protection system as option, also partly used for RGB output. This applies to SAA7124 only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-mercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductor sales office for more information ORDERING INFORMATION TYPE NUMBER SAA7124WP; SAA7125WP SAA7124HZ; SAA7125HZ SAA7124H; SAA7125H Note 1. LQFP64 package for V1 devices only. PACKAGE(1) NAME PLCC84 LQFP64 QFP80 DESCRIPTION plastic leaded chip carrier; 84 leads SAA7124; SAA7125 - Controlled rise and fall times of output syncs and blanking - Down-mode of DACs - LQFP64 (V1 devices only), QFP80 or PLCC84 package. GENERAL DESCRIPTION The SAA7124; SAA7125 encodes digital YUV video data to an NTSC or PAL CVBS plus RGB or alternatively...