SAA7183A Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET SAA7182A; SAA7183A Digital Video Encoder (EURO-DENC2) Preliminary specification Supersedes data of 1996 Sep 11 File under Integrated Circuits, IC22 1996 Oct 02 Philips Semiconductors Preliminary specification Digital Video Encoder (EURO-DENC2) Features - Monolithic CMOS 3.3 V device with 5 V input stages - Digital PAL/NTSC/SECAM encoder - System pixel frequency 13.5 MHz - Accepts MPEG decoded data on 8-bit wide input port. Input data format Cb, Y, Cr etc. “(CCIR 656) ” or Y and Cb, Cr on 16 lines - Three DACs for CVBS, Y and C operating at 27 MHz with 10 bit resolution - Three DACs for RGB operating at 27 MHz with 9 bit resolution, RGB sync on CVBS and Y - Analog multiplexing between internal RGB and external RGB on-chip - CVBS, Y, C and RGB output simultaneously - Closed captioning and teletext encoding including sequencer and filter - Line 23 wide screen signalling encoding - On-chip Cr, Y, Cb to RGB dematrix, including gain adjustment for Y and Cr, Cb, optionally to be by-passed for Cr, Y, Cb output on RGB DACs - Fast I2C-bus control port (400 k Hz) - Encoder can be master or slave - Programmable horizontal and vertical input synchronization phase - Programmable horizontal sync output phase - Internal Colour Bar Generator (CBG) - Overlay with Look-Up Tables (LUTs) 8 × 3 bytes - Macrovision Pay-per-View copy protection system as option, also used for RGB output. SAA7182A; SAA7183A This applies to SAA7183A only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-mercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductor sales office for more information - Controlled rise/fall times of output syncs and blanking - Down-mode of...