SAA7390 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET SAA7390 High performance pact Disc-Recordable (CD-R) controller Preliminary specification File under Integrated Circuits, IC01 1996 Jul 02 Philips Semiconductors Preliminary specification High performance pact Disc-Recordable (CD-R) controller CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 8 8.1 8.2 8.3 8.4 9 9.1 9.2 9.3 9.4 10 10.1 10.2 11 Features General Interface logic (CD-ROM operation) Hardware third-level error correction Interface logic (CD-R operation) DRAM buffer controller (256 kbytes × 8, 1 Mbyte × 8, 4 Mbytes × 8) Additional product support GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Input clock doubler Block encoder Front-end Track descriptor block Buffer manager MICROCONTROLLER INTERFACE Microprocessor interface status register Microcontroller interface mand register Microprocessor interrupts Microcontroller RAM organization FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS S2B UART registers SPI UART registers Track Descriptor Block (TDB) generation Miscellaneous control registers FRONT-END Minute-second frame addressing and header information Front-end status and control BUFFER MANAGER 11.1 11.2 11.3 11.4 11.5 11.6 11.7 12 13 14 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 16 17 17.1 17.2 17.3 17.4 18 19 Front-end to buffer manager interface Microcontroller to buffer manager interface ECC to buffer manager interface SCSI to buffer manager interface Miscellaneous buffer manager considerations Host interface related registers CDB2 related registers FRAME BUFFER ORGANIZATION SUMMARY OF CONTROL REGISTER MAP LIMITING VALUES OPERATING CHARACTERISTICS I2S-bus timing; data mode EIAJ timing; audio mode R-W timing (see Fig.17) C-flag timing (see Fig.18) S2B interface timing SPI interface timing Microprocessor interface Host interface DRAM interface (the SAA7390 is designed to operate with standard 70 ns DRAMs) PACKAGE OUTLINE...