Datasheet Details
| Part number | SAA7705H |
|---|---|
| Manufacturer | NXP Semiconductors |
| File Size | 1.81 MB |
| Description | Car radio Digital Signal Processor |
| Download | SAA7705H Download (PDF) |
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Overview: INTEGRATED CIRCUITS DATA SHEET SAA7705H Car radio Digital Signal Processor (DSP) Preliminary specification File under Integrated Circuits, IC01 1999 Aug 16 Philips Semiconductors Preliminary specification Car radio Digital Signal Processor (DSP) CONTENTS 1 1.1 1.2 2 3 4 5 6 7 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.5 8.5.1 8.5.2 8.5.
| Part number | SAA7705H |
|---|---|
| Manufacturer | NXP Semiconductors |
| File Size | 1.81 MB |
| Description | Car radio Digital Signal Processor |
| Download | SAA7705H Download (PDF) |
|
|
|
QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION FM and level information processing Signal path for level information Signal path from FMMPX input to IAC and stereo decoder Input sensitivity for FM and RDS signals AD input selection switch Interference absorption circuit Analog source selection and analog-to-digital conversion Input selection switches Signal flow of the AM, analog CD and TAPE inputs The analog CD block Pin VREFAD Pins VDACN1, VDACN2 and VDACP Supply of the analog inputs Analog outputs DACs Upsample filter Volume control Function of pin POM Power-off plop suppression The internal pin VREFDA Internal DAC current reference Supply of the analog outputs Clock circuit and oscillator Supply of the crystal oscillator The phase-locked loop circuit to generate the DSP clock and other derived clocks The clock block Synchronization with the core Equalizer accelerator circuit Introduction EQ circuit overview Controller and programming circuit 8.6 8.7 8.8 8.9 8.10 8.10.1 8.10.2 8.10.3 8.10.4 8.11 9 10 11 12 12.1 12.1.1 12.1.2 12.1.3 12.1.4 12.1.5 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.3 12.4 12.5 13 13.1 13.2 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 SAA7705H The DSP core External control pins and status register I2C-bus interface (pins SCL and SDA) I2S-bus inputs and outputs RDS decoder (pins RDSCLK and RDSDAT) Clock and data recovery Timing of clock and data signals Buffering of RDS data Buffer interface DSP reset LIMI
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