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SC16C2550 - Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder

This page provides the datasheet information for the SC16C2550, a member of the SC1 Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder family.

Datasheet Summary

Description

The SC16C2550 is a 2 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications.

Its principal function is to convert parallel data into serial data and vice versa.

The UART can handle serial data rates up to 5 Mbits/s.

Features

  • may be tailored by software to meet specific user requirements. An internal loop-back capability allows on-board diagnostics. Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2550 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature range, and is available in plastic PLCC44, LQFP48 and DIP40 packages. 2. Features s s s s s s s s s s s s s s s 2 channel UART 5 V, 3.3 V and 2.5 V operation Industrial temperature range Pin and.

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Datasheet preview – SC16C2550

Datasheet Details

Part number SC16C2550
Manufacturer NXP
File Size 603.56 KB
Description Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder
Datasheet download datasheet SC16C2550 Datasheet
Additional preview pages of the SC16C2550 datasheet.

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Full PDF Text Transcription

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SC16C2550 Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder Rev. 03 — 19 June 2003 Product data 1. Description The SC16C2550 is a 2 channel Universal Asynchronous Receiver and Transmitter (UART) used for serial data communications. Its principal function is to convert parallel data into serial data and vice versa. The UART can handle serial data rates up to 5 Mbits/s. The SC16C2550 is pin compatible with the ST16C2550. It will power-up to be functionally equivalent to the 16C2450. The SC16C2550 provides enhanced UART functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and RXRDY signals.
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