SJA2020 Description
2.1 Architectural overview The SJA2020 consists of an ARM7TDMI-S processor with real-time emulation support, the AMBA Advanced High-performance Bus (AHB) for interface to the on-chip memory controllers, a DTL bus (a universal Philips interface) for interface to the interrupt controller and three VLSI Peripheral Buses (VPB - a patible superset of ARMs AMBA advanced peripheral bus) for connection to the on-chip...
SJA2020 Applications
- a patible superset of ARMs AMBA advanced peripheral bus) for connection to the on-chip peripherals clustered in so-called subsystems. The SJA2020 configures the