SSTUM32865 Datasheet | NXP Semiconductors

description The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to acmodate high-density Dual In-line Memory Module (DIMM) designs. The SSTUM32865 also integrates a parity function, which accepts a parity bit from the memory controller, pares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). It further offers added features over the JEDEC standard register in that it is permanently configured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUM32865 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward patible to the JEDEC standard register. The SSTUM32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which, while requiring a minimum 9 mm × 13 mm of board space, allows for adequate signal routing and escape using conventional card technology. 2. Features I 28-bit data register supporting DDR2 I Fully pliant to JEDEC standard for SSTUB32865 I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 × SSTUB32864 or 2 × SSTUB32866) I Parity checking function across 22 input data bits I Parity out signal I Controlled multi-impedance output impedance drivers enable optimal signal integrity and speed I Meets or exceeds SSTUB32865 JEDEC standard speed performance I Supports up to...