SSTVF16857 Datasheet | NXP Semiconductors

FEATURES - Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) - Optimized for PC 2700 DDR (Double Data Rate) SDRAM - Suitable for PC1600/PC2100 DDR SDRAM applications - Suitable for PC3200 applications when used at VDD = 2.6 V - Inputs patible with JESD8-9 SSTL_2 specifications. - Flow-through architecture optimizes PCB layout - ESD classification testing is done to JEDEC Standard JESD22. - Latch-up testing is done to JEDEC Standard JESD78, which - Full DDR300/333/400 solution @ 2.5V when used with PCKV857 - Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages - Superior VREF noise rejection DESCRIPTION The SSTVF16857 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5- VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTVF16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 166 MHz will have a burst rate of 333 MT/s (mega-transfers per second). The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTVF16857 is intended to be used for SSTL_2 input and output signals. The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be patible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the...