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SSTVF16859 Description

All inputs are patible with the JEDEC standard for SSTL_2 with Vref normally at 0.5 × VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II patible, which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero.