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INTEGRATED CIRCUITS
DATA SHEET
TDA1305T Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
Preliminary specification Supersedes data of September 1994 File under Integrated Circuits, IC01 1995 Dec 08
Philips Semiconductors
Preliminary specification
Stereo 1fs data input up-sampling filter with bitstream continuous dual DAC (BCC-DAC2)
FEATURES • Easy application • 16fs Finite-duration Impulse-Response (FIR) filter incorporated • Selectable system clock (fsys) 256fs or 384fs • I2S-bus serial input format (at fsys = 256fs) or LSB fixed 16, 18 or 20 bits serial input mode (at fsys = 384fs) • Slave-mode clock system • Cascaded 4-stage digital filter incorporating 2-stage FIR filter, linear interpolator and sample-and-hold • Smoothed transitions before and a
TDA1305T Datasheet
