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TDA8366 - I2C-bus controlled PAL/NTSC TV processor

General Description

The TDA8366 is an I2C-bus controlled PAL/NTSC TV processor.

The circuit has been designed for use with the baseband chrominance delay line TDA4665 and for DC-coupled vertical and East-West (EW) output stages.

Key Features

  • Multistandard vision IF circuit (positive and negative modulation).
  • Video identification circuit in the IF circuit which is independent of the synchronization for stable On Screen Display (OSD) under ‘no-signal’ conditions.
  • Source selection with 2 Colour Video Blanking Synchronization (CVBS) inputs and a Y/C (or extra CVBS) input.
  • Output signals of the video switch circuit for the teletext decoder and a Picture-In-Picture (PIP) processor.
  • Integrated.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS DATA SHEET TDA8366 I2C-bus controlled PAL/NTSC TV processor Objective specification File under Integrated Circuits, IC02 January 1995 Philips Semiconductors Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processor FEATURES • Multistandard vision IF circuit (positive and negative modulation) • Video identification circuit in the IF circuit which is independent of the synchronization for stable On Screen Display (OSD) under ‘no-signal’ conditions • Source selection with 2 Colour Video Blanking Synchronization (CVBS) inputs and a Y/C (or extra CVBS) input • Output signals of the video switch circuit for the teletext decoder and a Picture-In-Picture (PIP) processor • Integrated chrominance trap and bandpass filters (automatically calibrate