NXP Semiconductors UDA1352TS
The UDA1352TS is a single-chip IEC 60958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques. By default, the DAC output is muted when the decoder is out-of-lock. The UDA1352TS has IEC 60958 input to the DAC only and is in SSOP28 package.| Part No. | UDA1352TS |
|---|---|
| Datasheet | UDA1352TS Download |
| Manufacturer |  NXP Semiconductors |
| Description | 48 kHz IEC 60958 audio DAC |
| Buy | Stock & Price |
FEATURES
General Control IEC 60958 input Digital sound processing and DACAPPLICATIONS
GENERAL DESCRIPTION
ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONALDESCRIPTION
Clock regeneration and lock detection Mute Auto mute Data path Control L3-BUSDESCRIPTION
General Device addressing Register addressing Data write mode Data read mode Initialization string I2C-BUSDESCRIPTION
Characteristics of the I2C-bus Bit transfer Byte transfer Data transfer Start and stop conditions Acknowledgment Device address Register address Write and read data Write cycle Read cycle Preliminary specification UDA1352TS 11 11.1 11.2 11.3 11.4 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 19.5 20 21 22 SPDIF SIGNAL FORMAT SPDIF channel encoding SPDIF hierarchical layers for audio data SPDIF hierarchical layers for digital data Timing characteristics REGISTER MAPPING SPDIF mute setting (write) Power-down settings (write) Volume contro...
