UJA1065 Datasheet | NXP Semiconductors

High-speed CAN/LIN fail-safe system basis chip Rev. 07 - 25 February 2010 Product data sheet 1. General description The UJA1065 fail-safe System Basis Chip (SBC) replaces basic discrete ponents that are mon in every Electronic Control Unit (ECU) with a Controller Area Network (CAN) and a Local Interconnect Network (LIN) interface. The fail-safe SBC supports all networking applications that control various power and sensor peripherals by using high-speed CAN as the main network interface and LIN as a local sub-bus. The fail-safe SBC contains the following integrated devices: - High-speed CAN transceiver, interoperable and downward patible with CAN transceivers TJA1041 and TJA1041A, and patible with the ISO 11898-2 standard and the ISO 11898-5 standard (in preparation) - LIN transceiver pliant with LIN 2.0 and SAE J2602, and patible with LIN 1.3 - Advanced independent watchdog - Dedicated voltage regulators for microcontroller and CAN transceiver - Serial peripheral interface (full duplex) - Local wake-up input port - Inhibit/limp-home output port In addition to the advantages of integrating these mon ECU functions in a single package, the fail-safe SBC offers an intelligent bination of system-specific functions such as: - Advanced low-power concept - Safe and controlled system start-up behavior - Advanced fail-safe system behavior that prevents any conceivable deadlock - Detailed status reporting on system and subsystem levels The UJA1065 is designed to be used in bination with a microcontroller that incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is always started up in a defined manner. In failure situations, the fail-safe SBC will maintain microcontroller functionality for as long as possible to provide full monitoring and a software-driven fall-back operation. The UJA1065 is designed for 14 V single power supply architectures and for 14 V and 42 V dual power supply architectures. NXP...