XA-SCC Datasheet | NXP Semiconductors

DESCRIPTION The XA-SCC device is a member of Philips’ XA (e Xtended Architecture) family of high performance 16-bit single-chip microcontrollers. The XA-SCC includes a plete onboard DRAM controller capable of supporting up to 32Mega Bytes of DRAM. The XA-SCC device bines many powerful munications oriented peripherals on one chip. 4 Full Function SCC’s, 8 DMA channels (2 per SCC), hardware autobaud up to 921.6Kbps, IDL TDM interface, two timers/counters, 1 watchdog timer, and multiple general purpose I/O ports. It is suited for many high performance embedded munications functions, including ISDN terminal adaptors and Asynchronous Muxes. - Memory controller also generates 6 chip selects to support SRAM, ROM, Flash, EPROM, peripheral chips, etc. without external glue. - Supports off-chip addressing up to 32 MB (2 x 2- - 24 address spaces) in Harvard architecture, or 16MB in unified memory configuration. - A clock output reference “Clk Out” is added to simplify external bus interfacing. - High performance 8-channel DMA Controller offloads the CPU for moving data to/from SCC’s and memory. - Two standard counter/timers with enhanced features (same as XA-G3 T0, T1). Both timers have a toggle output capability. SPECIFIC FEATURES OF THE XA-SCC range, available in 100 pin LQFP package. - 3.3V to 5.5V operation to 30MHz over the industrial temperature - 4 onboard SCC’s for 2B+D plus Asynch port, or any bination of 4 sync/async ports. Industry standard IDL and SCP interfaces for glueless connection to U-Chip or S/T chip. Sync data rates to 4Mbps. Asynch data rates to 921.6Kbps with/without autobaud. - Watchdog timer. - Seven standard software interrupts, plus four High Priority Software Interrupts, plus 7 levels of Hardware Event Interrupts. - Active low reset output pin indicates all internal reset occurrences (watchdog reset and the RESET instruction). A reset source register allows program determination of the cause of the most recent reset. - plete onboard DRAM...