NT5SV8M16CT Overview
These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC’s advanced 128Mbit single transistor CMOS DRAM process technology. The device is designed to ply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically.
NT5SV8M16CT Key Features
- High Performance
- 7K 3 CL=2 fCK tCK tAC t Clock Frequency Clock Cycle Clock Access Time1 Clock Access
- 75B, CL=3 133 7.5
- 8B, CL=2 100 10
- Single Pulsed RAS Interface
- Fully Synchronous to Positive Clock Edge
- Four Banks controlled by BS0/BS1 (Bank Select)
