NT5CC128M16HP
Description
The 2Gb Double-Data-Rate-3 (DDR3(L)) H-die DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs.
Key Features
- 1.35V -0.067V/+0.1V & 1.5V ± 0.075V (JEDEC Standard Power Supply) * *
- 8 Internal memory banks (BA0- BA2) Differential clock input (CK, ) Programmable Latency: 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 *
- WRITE Latency (CWL): 5,6,7,8,9 and 10 POSTED CAS ADDITIVE Programmable Additive Latency (AL): 0, CL-1, CL-2 clock * * *
- Programmable Sequential / Interleave Burst Type Programmable Burst Length: 4, 8 8n-bit prefetch architecture Output Driver Impedance Control * * * * * * * * *
- Through ZQ pin (RZQ:240 ohm±1%) Differential bidirectional data strobe Internal(self) calibration:Internal self calibration OCD Calibration Dynamic ODT (Rtt_Nom & Rtt_WR) Auto Self-Refresh Self-Refresh Temperature RoHS Compliance and Halogen free Packages: 96-Balls BGA for x16 components Operating temperature Commerical grade (0℃≦TC≦95℃) For -BE,-CG,-DI, -EK, -FL Industrial grade (-40℃≦TC≦95℃) For -CGI,-DII 1 REV 1.4 02 /2013 © NANYA TECHNOLOGY CORP. All rights reserved
