NT5SV64M4AT Overview
These synchronous devices achieve high-speed data transfer rates of up to 133MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTC’s advanced 256Mbit single transistor CMOS DRAM process technology. The device is designed to ply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically.
NT5SV64M4AT Key Features
- High Performance
- 7K 3 CL=2 fCK tCK tAC tAC Clock Frequency Clock Cycle Clock Access Time 1 133 7.5
- 5.4 -75B, CL=3 133 7.5
- 5.4 -8B, CL=2 100 10
- 6 Units MHz ns ns ns
