NT5TU64M16GG Datasheet PDF (1Gb DDR2 SDRAM) | Download Nanya NT5TU64M16GG

NT5TU64M16GG - 1Gb DDR2 SDRAM

This page provides the datasheet information for the NT5TU64M16GG, a member of the NT5TU128M8GE 1Gb DDR2 SDRAM family.

Description

The 1giga bit (1Gb) Double-Data-Rate-2 (DDR2) DRAMs is a high-speed CMOS Double Data Rate 2 SDRAM containing 1,073,741,824 bits.

It is internally configured as an octal-bank DRAM.

The 1Gb chip is organized as 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device.

Features

(1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a sou.

Datasheet Details

Part number	NT5TU64M16GG
Manufacturer	Nanya
File Size	2.47 MB
Description	1Gb DDR2 SDRAM
Datasheet	NT5TU64M16GG Datasheet
Additional preview pages of the NT5TU64M16GG datasheet.

📁 Similar Datasheet

NT50198 - TFT-LCD 3-Channel Charge Pump Power IC (Novatek)

NT51007D - 1200CH TFT LCD Source Driver (Novatek)

NT51021 - 1803CH Source Driver (Novatek)

NT511740C5J - Fast Page Mode with EDO DRAM (Nanya Technology)

NT511740D0J - Fast Page Mode DRAM (Nanya Technology)

NT511740D5J - CMOS with Rxtended Data Out (Nanya Technology)

NT512D64S8HB0G - 184 pin Unbuffered DDR DIMM (ETC)

NT512D64S8HB1G - 184 pin Unbuffered DDR DIMM (ETC)

NT512D64S8HB1GY - 184 pin Unbuffered DDR DIMM (ETC)

NT512D72S8PB0G - 184 pin Unbuffered DDR DIMM (ETC)

Full PDF Text Transcription

Click to expand full text

NT5TU128M8GE / NT5TU64M16GG 1Gb DDR2 SDRAM Feature CAS Latency Frequency -3C/3CI Speed Bins (DDR2-667-CL5) Parameter Clock Frequency Min. Max. (DDR2-800-CL5) Min. Max. (DDR2-1066-CL7) Min. Max. (DDR2-1066-CL6) Min. Max. tCK(Avg.) MHz ns ns ns ns ns ns ns ns ns -AC/ACI/ACL -BE -BD Units 125 15 15 60 40 5 3.75 3 - 333 70K 8 8 8 - 125 12.5 12.5 57.5 40 5 3.75 2.5 2.5 - 400 70K 8 8 8 8 - 125 12.5 12.5 57.5 40 5 3.75 2.5 2.5 1.875 533 70K 8 8 8 8 8 125 11.25 11.25 56.25 40 5 3.75 2.5 1.875 1.875 533 70K 8 8 8 8 8 tRCD tRP tRC tRAS tCK(Avg.)@CL3 tCK(Avg.)@CL4 tCK(Avg.)@CL5 tCK(Avg.)@CL6 tCK(Avg.)@CL7 *The timing specification of high speed bin is backward compatible with low speed bin  VDD=VDDQ=1.8V ± 0.1V Voltage JEDEC standard 1.

Published: Oct 13, 2014 |