DS92LV3221 Overview
The DS92LV3221 (SER) serializes a 32-bit data bus into 2 embedded clock LVDS serial channels for a data payload rate up to 1.6 Gbps over cables such as CATx, or backplanes FR-4 traces. The panion DS92LV3222 (DES) deserializes the 2 LVDS serial data channels, de-skews channel-to-channel delay variations and converts the LVDS data stream back into a 32-bit LVCMOS parallel data bus. On-chip data...
DS92LV3221 Key Features
- Wide Operating Range Embedded Clock SER/DES
- Up to 32-bit parallel LVCMOS data
- 20 to 50 MHz parallel clock
- Up to 1.6 Gbps application data paylod Simplified Clocking Architecture
- No separate serial clock line
- No reference clock required
- Receiver locks to random data On-chip Signal Conditioning for Robust Serial Connectivity
- Transmit Pre-Emphasis
- Data randomization
- DC-balance encoding
